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| RFD14N06L, RFD14N06LSM, RFP14N06L Data Sheet July 1999 File Number 4088.3 14A, 60V, 0.100 Ohm, Logic Level, N-Channel Power MOSFETs These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA09870. Features * 14A, 60V * rDS(ON) = 0.100 * Temperature Compensating PSPICE(R) Model * Can be Driven Directly from CMOS, NMOS, and TTL Circuits * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER RFD14N06L RFD14N06LSM RFP14N06L PACKAGE TO-251AA TO-252AA TO-220AB BRAND 14N06L 14N06L FP14N06L Symbol D G NOTE: When ordering, use the entire part number. Add the suffix 9A, to obtain the TO-252AA variant in tape and reel, i.e. RFD14N06LSM9A. S Packaging JEDEC TO-251AA SOURCE DRAIN GATE GATE SOURCE JEDEC TO-252AA DRAIN (FLANGE) DRAIN (FLANGE) JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 6-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFD14N06L, RFD14N06LSM, RFP14N06LS Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N06L, RFD14N06LSM, RFP14N06LS 60 60 10 14 Refer to Peak Current Curve Refer to UIS Curve 48 0.32 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, Figure 13 VGS = VDS, ID = 250A, Figure 12 VDS = 48V, VGS = 0V VGS = 10V ID = 14A, VGS = 5V VDD = 30V, ID = 7A, RL = 4.28, VGS = 5V, RGS = 0.6 Figures 10, 18, 19 TC = 25oC TC = 150oC MIN 60 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 48V, ID = 14A, RL = 3.43 Figures 20, 21 TO-251 and TO-252 TO-220 TYP 13 24 42 16 670 185 50 MAX 2 1 50 100 0.100 60 100 40 25 1.5 3.125 100 80 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Case Thermal Resistance Junction-to-Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA VDS = 25V, VGS = 0V, f = 1MHz Figure 14 Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 14A ISD = 14A, dISD/dt = 100A/s MIN TYP MAX 1.5 125 UNITS V ns 6-2 RFD14N06L, RFD14N06LSM, RFP14N06L Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 12 0.8 0.6 0.4 0.2 0 Unless Otherwise Specified 16 8 4 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 THERMAL IMPEDANCE ZJC, NORMALIZED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA + TA 10-2 10-1 10-3 t, RECTANGULAR PULSE DURATION (s) 100 101 PDM 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TC = 25oC TJ = MAX RATED IDM, PEAK CURRENT CAPABILITY (A) 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: ID, DRAIN CURRENT (A) 10 100s 175 - T C I = I 25 --------------------- 150 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 VGS = 5V VGS = 10V TC = 25oC 10ms 100ms DC 200 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 6-3 RFD14N06L, RFD14N06LSM, RFP14N06L Typical Performance Curves 50 IAS, AVALANCHE CURRENT (A) Unless Otherwise Specified (Continued) 35 30 ID, DRAIN CURRENT (A) 25 20 15 10 5 0 VGS = 3V VGS = 2.5V 0 1.5 6.0 3.0 4.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 7.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. TC = 25oC VGS = 10V VGS = 5V VGS = 4.5V VGS = 4V STARTING TJ = 25oC 10 STARTING TJ = +150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) 1 If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) 35 30 25 20 15 10 5 0 0 rDS(ON) , DRAIN TO SOURCE ON RESISTANCE (m) VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 25oC -55oC 175oC 250 200 ID = 7A 150 ID = 14A ID = 28A 100 ID = 3.5A 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5 0 2.5 3.0 3.5 4.0 4.5 VGS , GATE TO SOURCE VOLTAGE (V) 5.0 FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 160 VDD = 25V, ID = 14A, RL = 1.78 140 SWITCHING TIME (ns) 120 100 80 tf 60 40 td(ON) 20 0 0 10 20 30 40 50 tr NORMALIZED DRAIN TO SOURCE ON RESISTANCE td(OFF) 2.5 VGS = 5V, ID = 14A 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 RGS, GATE TO SOURCE RESISTANCE () TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. SWITCHING TIME vs GATE TO SOURCE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 6-4 RFD14N06L, RFD14N06LSM, RFP14N06L Typical Performance Curves 2.0 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE Unless Otherwise Specified (Continued) 2.0 ID = 250A THRESHOLD VOLTAGE NORMALIZED GATE 1.5 1.5 1.0 1.0 0.5 0.5 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 800 FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 60 VDS, DRAIN-SOURCE VOLTAGE (V) 10 VDD = BVDSS 45 VDD = BVDSS 7.5 VGS, GATE-SOURCE VOLTAGE (V) CISS C, CAPACITANCE (pF) 600 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS 200 CRSS 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 400 30 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.57 IG(REF) = 0.4mA VGS = 5V I G ( REF ) I G ( REF ) 5.0 15 2.5 0 0 20 --------------------I G ( ACT ) t, TIME (ms) 80 --------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS 6-5 RFD14N06L, RFD14N06LSM, RFP14N06L Test Circuits and Waveforms (Continued) tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD VDS VGS = 10V Qg(5) D VGS VGS = 5V Qg(TOT) 12V BATTERY 0.2F 50k 0.3F SAME TYPE AS DUT G DUT VGS = 1V 0 S Qg(TH) VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS 6-6 RFD14N06L, RFD14N06LSM, RFP14N06L PSPICE Electrical Model .SUBCKT RFP14N06L 2 1 3 ; CA 12 8 1.464e-9 CB 15 14 1.64e-9 CIN 6 8 6.17e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.68e-9 LSOURCE 3 7 5.35e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 12 GATE 1 rev 9/15/94 DPLCAP 10 RSCL1 RSCL2 + 51 5 51 6 8 VTO 6 + 21 MOS1 RIN CIN 8 RSOURCE 7 LSOURCE 3 SOURCE ESCL 50 ESG + EVTO 9 20 + 18 8 LGATE RGATE RDRAIN 16 11 EBREAK 17 18 MOS2 + DBODY DBREAK 5 LDRAIN DRAIN 2 S1A 13 8 S1B CA + EGS 6 8 14 13 S2A 15 S2B 13 CB EDS + 14 5 8 IT RBREAK 17 18 RVTO 19 VBAT + RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 33.1e-3 RGATE 9 20 5.85 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 14.3e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.485 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))} .MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8) .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. 6-7 RFD14N06L, RFD14N06LSM, RFP14N06L All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6-8 |
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